Clock and Data Recovery/Structures and types of CDRs

At the receiving end of a data transmission link, the received signal is amplified, filtered and equalized. Then a “slicer” circuit reshapes it and retains just the level transitions and the levels that represent the nominal values of the received signal in that interval between two consecutive transitions. The CDR processes the “sliced” signal

• to extract the clock signal embedded in its transitions (clock recovery) and
• to sample and retime the pulses of the “sliced” signal (data recovery).

Clock recover circuits include:

• the phase locked loop architecture (PLL) -- the most common method of clock recovery
• the synchronous oscillator—much less common, but which may claim, in certain cases, some advantages over PLL [ 1 ]
• the gated oscillator, that resembles the synchronous oscillator, and that is useful when very fast acquisition is needed and other performances can be traded off in return for it. [ 2 ]

Many good books are available, with theory and practical examples, like. [ 3 ]

It is useful however, in order to get the best out of them, to have the ability to recognize in each case the fundamental architecture, that is the "Control Systems" block diagram that corresponds to the actual circuit.

Contents

• 1 Importance of good reference models
• 2 Essential parts of a CDR
• 3 Order and type of a CDR
  • 3.1 Order
  • 3.2 Type
  • 3.3 Loop type and steady state error
    • 3.3.1 General case
    • 3.3.2 1st order loop
    • 3.3.3 2nd order loop

    Importance of good reference models

    The function of a CDR is a relatively simple one. The architectures possible for it are, accordingly, just a few and simple ones (actually just three!). It is nonetheless important to have a good knowledge of those architectures and a good understanding of their mathematical descriptions because these models are the best tools for the engineer that must deal with CDRs.

    Starting from the definition and specification of (a communication system and of its) CDR(s), and all the way through all the different engineering tasks that logically follow (like design, verification, validation, manufacturing tests, failure analysis, system operation and maintenance), those models can be an invaluable reference for the engineer. He will need them to imagine, specify, design, check, measure and interpret the behavior of a CDR.

    The actual implementation of the CDR may differ from the neat, simple structure that the model depicts. Complex digital blocks, DLLs, DSPs may render the analogy difficult to detect, but the fundamental signals and operation of the CDR can not differ. Yielding to the temptation of forgetting the models is a very risky and error prone short cut.

    The essential signals and blocks of the architecture must be clearly identified in the actual system. The use of the reference model will then be the best way to make sure that all aspects of the CDR operation are identified and taken into consideration.

    The CDR is always designed with the architecture of a PLL (with the obvious addition of the regeneration block, where the received pulses are re-sampled with the local clock). Let’s study the PLL, that is the essential part. It should be kept in mind that such PLL will be specialized for application inside a CDR.

    

    The reference model of a PLL in a CDR: unity feedback, first or second order, type 1 or 2.

    The PLLs inside CDRs are in all cases of the unity feedback kind. The input of the circuit is the phase of a reference signal (a clock or a serial data signal) and the output is the phase of a signal (a serial data stream or a simple clock). The output is locked -as much as the circuit can- to the input signal. The input signal is contrasted with the output signal in a phase comparator, whose output is the error signal. The error signal is processed and then used to control another circuit block that produces the output clock signal.

    It may be remarked that the output clock is always phase locked to the input signal, and that it is used to regenerate the input signal in the slave CDRs. In the phase aligner CDRs it is the local clock that regenerates (a phase aligned version of) the received signal.

    Essential parts of a CDR

    It is important to identify the essential parts (listed below) of the CDR system but also to identify where the received signal and the local clock fit in the architecture. Either one (the received signal or the local clock) may act as input, while the other would simply act as an internal input signal inside the block called “Controlled element” (the block that generates the output signal of the PLL).

    The received signal acts as reference input for the PLL when the PLL function is to generate a clock slaved to the received signal itself.
    The local clock acts instead as reference signal for the PLL when the PLL function is simply to “phase align” the received signal to it, in the cases where the received signal timing is derived from the local clock itself (following a short loop inside a unique clock domain where the local clock is master).

    The list of the parts that shall be clearly identified in the CDR are:

    1. the phase information (carried by the level transitions) of the received signal
    2. the phase information (carried by the level transitions) of the local clock
    3. the phase comparator that measures the relative phase of the local clock with respect to the phase of (a signal related to) the received signal
    4. an integration block (1/s in the language of Control Systems) or an accumulator if the implementation is of the discrete time type. It makes the control loop able to squeeze down to zero the steady state frequency error (and to a negligible value the corresponding phase error)
    5. the regeneration of (a signal related to) the received signal by the local clock.

    Order and type of a CDR

    Order

    The order of a control loop (causal, linear and time invariant in our models of CDRs) is the order of the differential equation that describes it.
    In the language of control systems, the order is the number of poles of the (open or closed loop) system transfer function.

    • 1st order systems are unconditionally stable, are characterised by one parameter only and represent a good reference model for the simplest CDR PLLs.
    • 2nd order systems are unconditionally stable, are characterised by two parameters and represent a good reference model for the other, more complex, CDR PLLs.
    • 3rd and higher order systems are not of practical use in the study of CDRs. They may be unstable in some conditions and, moreover, they are more complex to use but do not offer a better behavior for CDR use than the 2nd order systems. ( Some complexity beyond the simple 2nd order system can be useful to model more accurately some parasitic effects of a CDR circuit, but not to design nor to model performances within the range of functionality of the CDR).

    Type

    The type of a control loop is the number of poles of the open loop transfer function in the origin (that is, how many times the factor 1/s appears in the open loop transfer function).

    The type of a loop tells how well the loop itself is able to track a deviation of its input signal from the nominal value.

    (A CDR can operate with a small phase (= sampling time) error without deterioration of performances, provided the error is small enough: a few degrees of jitter around the optimum sampling time do not significantly deteriorate the bit error rate!)

    • Type 0 systems are able to track a step function ( a phase deviation of the input from the nominal phase expected by the circuit itself) with a small, but finite error. A type 0 PLL can not track at all a linear ramp of phase variation in the received signal (that is a step change of the frequency of the received signal with respect to the frequency of the -free running- local oscillator!). Therefore they are not of large use for CDRs.
    • Type 1 systems are able to track signals that exhibit a step change of phase, without steady-state error. They are not able to track unit ramp inputs without a finite error, though.
      CDRs are very often type 1 systems, because they can be designed to phase lock:
      1. with zero phase error when there is no frequency (just phase) difference
      2. with a very small phase error when the master clock embedded in a received signal stream and the free running frequency of the local oscillator are close together.
    • Type 2 systems are able to track signals with a frequency different from the their free running frequency, without steady-state error.
      (As type 2 implies by definition at least 2nd order or higher, just the type 2 of 2nd order is to consider).
      In practice the 2nd order type 2 architecture is used because a constant frequency mismatch can be tracked with zero error independently of the loop gain.
      This is unfortunately accompanied by a softer rejection of the input jitter (= input signal noise) at high frequencies.
      When the loop gain is variable in a very wide range (because of a bang-bang phase detector) and/or especially when a VCO with poor accuracy must be used, this architecture is preferred.

    Loop type and steady state error

    General case

    A unity feedback system (all PLL for CDRs are unity feedback) exhibits a finite long term error ( steady state error ) between input and output when the input (besides sinusoids of any frequency and magnitude), includes a constant, or a step function, or a ramp function, etc., depending on the type of the system.

    The steady state error, when it exists and is finite and non-zero, can be computed from the open loop transfer function:

    GH = K ∏ i = 1 m ( s − z i ) ∏ i = 1 n ( s − p i ) ^(s-z_)><\prod _^(s-p_)>>>

    using the following table, that resumes the most important formulas for the systems representing CDR architectures:

    Steady-state error for stable type 1 unity-feedback systems

    System type ↓ and input signal →	Unit step	Unit ramp	Unit parabola
    Type 0	1 1 + K ∏ i = 1 m ( 0 − z i ) ∏ i = 1 n ( 0 − p i ) ^(0-z_)><\prod _^(0-p_)>>>>>	∞	∞
    Type 1	0	∏ i = 1 n ( 0 − p i ) K ∏ i = 1 m ( 0 − z i ) ^(0-p_)>^(0-z_)>>>	∞
    Type 2	0	0	∏ i = 1 n ( 0 − p i ) K ∏ i = 1 m ( 0 − z i ) ^(0-p_)>^(0-z_)>>>